4060 "ثنائي ذو 14 مرحلة مموجة"

The 4060 is a 14-stage ripple-carry binary counter/divider and oscillator with three oscillator terminals (RS, REXT and CEXT), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset input (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. The clock input?s
Schmitt-trigger action makes it highly tolerant to slower clock rise and fall times. The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of other input conditions. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
Features?
? Tolerant of slow clock rise and fall times
? Fully static operation
? 5 V, 10 V, and 15 V parametric ratings
? Standardized symmetrical output characteristics
? Inputs and outputs are protected against electrostatic effects
? Specified from ?40 ?C to 85 ?C
? Complies with JEDEC standard JESD 13-B

تحميل ورقة البيانات